** ADVISORY **

SAN JOSE, Calif.- June 8, 2001 - Novas, the leader in debug systems for complex chip designs, today announced it is providing free one hour seminars on debugging Verilog, VHDL, and mixed-language designs at the Design Automation Conference. The seminars will show design and verification engineers how to accelerate their understanding of complex chip designsdesign intent and significantly reduce the time required for debug. Participants will see how Debussy®, the leading Verilog and VHDL debug system, helps them locate, isolate, and understand the causes of bugs. The sessions will also show new technology that helps teams involved in design reuse and IP integration more easily preserve and share design knowledge.

WHAT: Seminar Series "Accelerating Understanding for Faster Debug and Smart Reuse"

WHEN: June 18 - 21

WHERE: Novas Suite #6007, The Design Automation Conference at the Las Vegas Convention Center

Registration
To participate in the seminars or to learn about upcoming Novas events, please go to http://www.novas.com.

About Novas
Novas is the leader in debug systems for complex chip designs. The Company's Debussy® Total Debug system manages the design debug process for system-on-chip integrated circuits, dramatically reducing the time it takes to locate, isolate, and understand the causes of unexpected design behavior. Debussy increases designer and design team productivity during the time-intensive verification and debug phases. Novas has over seven thousand systems in use at hundreds of customer sites worldwide.

Novas is located at 2025 Gateway Place, Suite 480, San Jose, CA 95110.
Phone: 408-467-7888 or 888-NOVAS-38, Fax: 408-467-7889. For more information visit www.novas.com or send email to info@novas.com.

Press Contacts:

Maggie Albrecht (Novas)
Maggie@novas.com
(408) 467-7867

Eileen Elam (KJ Communications)
KjcomE@cs.com
(650-917-1488